? semiconductor components industries, llc, 2000 august, 2000 rev. 4 1 publication order number: mc14518b/d mc14518b dual up counters the mc14518b dual bcd counter and the mc14520b dual binary counter are constructed with mos pchannel and nchannel enhancement mode devices in a single monolithic structure. each consists of two identical, independent, internally synchronous 4stage counters. the counter stages are type d flipflops, with interchangeable clock and enable lines for incrementing on either the positivegoing or negativegoing transition as required when cascading multiple stages. each counter can be cleared by applying a high level on the reset line. in addition, the mc14518b will count out of all undefined states within two clock periods. these complementary mos up counters find primary use in multistage synchronous or ripple counting applications requiring low power dissipation and/or high noise immunity. ? diode protection on all inputs ? supply voltage range = 3.0 vdc to 18 vdc ? internally synchronous for high internal and external speeds ? logic edgeclocked design e incremented on positive transition of clock or negative transition on enable ? capable of driving two lowpower ttl loads or one lowpower schottky ttl load over the rated temperature range maximum ratings (voltages referenced to v ss ) (note 2.) symbol parameter value unit v dd dc supply voltage range 0.5 to +18.0 v v in , v out input or output voltage range (dc or transient) 0.5 to v dd + 0.5 v i in , i out input or output current (dc or transient) per pin 10 ma p d power dissipation, per package (note 3.) 500 mw t a operating temperature range 55 to +125 c t stg storage temperature range 65 to +150 c t l lead temperature (8second soldering) 260 c 2. maximum ratings are those values beyond which damage to the device may occur. 3. temperature derating: plastic ap and d/dwo packages: 7.0 mw/ c from 65 c to 125 c this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open. http://onsemi.com a = assembly location wl, l = wafer lot yy, y = year ww, w = work week device package shipping ordering information mc14518bcp pdip16 2000/box mc14518bdw soic16 47/rail marking diagrams 1 16 pdip16 p suffix case 648 mc14518bcp awlyyww mc14518bdwr2 soic16 1000/tape & reel soic16 dw suffix case 751g 1 16 14518b awlyyww 1. for ordering information on the eiaj version of the soic packages, please contact your local on semiconductor representative. soeiaj16 f suffix case 966 1 16 mc14518b alyw mc14518bf soeiaj16 see note 1. mc14518bfel soeiaj16 see note 1.
mc14518b http://onsemi.com 2 pin assignment 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 q1 b q2 b q3 b r b v dd c b e b q0 b q1 a q0 a e a c a v ss r a q3 a q2 a block diagram v dd = pin 16 v ss = pin 8 3 4 5 6 14 13 12 11 c c r r q3 q2 q1 q0 q3 q2 q1 q0 clock 1 2 clock enable enable 7 9 10 15 truth table clock enable reset action 1 0 increment counter 0 0 increment counter x 0 no change x 0 no change 0 0 no change 1 0 no change x x 1 q0 thru q3 = 0 x = don't care
mc14518b http://onsemi.com 3 ????????????????????????????????? ????????????????????????????????? electrical characteristics (voltages referenced to v ss ) v dd 55 c 25 c 125 c characteristic symbol v dd vdc min max min typ (4.) max min max unit output voltage a0o level v in = v dd or 0 v ol 5.0 10 15 e e e 0.05 0.05 0.05 e e e 0 0 0 0.05 0.05 0.05 e e e 0.05 0.05 0.05 vdc a1o level v in = 0 or v dd v oh 5.0 10 15 4.95 9.95 14.95 e e e 4.95 9.95 14.95 5.0 10 15 e e e 4.95 9.95 14.95 e e e vdc input voltage a0o level (v o = 4.5 or 0.5 vdc) (v o = 9.0 or 1.0 vdc) (v o = 13.5 or 1.5 vdc) v il 5.0 10 15 e e e 1.5 3.0 4.0 e e e 2.25 4.50 6.75 1.5 3.0 4.0 e e e 1.5 3.0 4.0 vdc a1o level (v o = 0.5 or 4.5 vdc) (v o = 1.0 or 9.0 vdc) (v o = 1.5 or 13.5 vdc) v ih 5.0 10 15 3.5 7.0 11 e e e 3.5 7.0 11 2.75 5.50 8.25 e e e 3.5 7.0 11 e e e vdc output drive current (v oh = 2.5 vdc) source (v oh = 4.6 vdc) (v oh = 9.5 vdc) (v oh = 13.5 vdc) i oh 5.0 5.0 10 15 3.0 0.64 1.6 4.2 e e e e 2.4 0.51 1.3 3.4 4.2 0.88 2.25 8.8 e e e e 1.7 0.36 0.9 2.4 e e e e madc (v ol = 0.4 vdc) sink (v ol = 0.5 vdc) (v ol = 1.5 vdc) i ol 5.0 10 15 0.64 1.6 4.2 e e e 0.51 1.3 3.4 0.88 2.25 8.8 e e e 0.36 0.9 2.4 e e e madc input current i in 15 e 0.1 e 0.00001 0.1 e 1.0 m adc input capacitance (v in = 0) c in e e e e 5.0 7.5 e e pf quiescent current (per package) i dd 5.0 10 15 e e e 5.0 10 20 e e e 0.005 0.010 0.015 5.0 10 20 e e e 150 300 600 m adc total supply current (5.) (6.) (dynamic plus quiescent, per package) (c l = 50 pf on all outputs, all buffers switching) i t 5.0 10 15 i t = (0.6 m a/khz) f + i dd i t = (1.2 m a/khz) f + i dd i t = (1.7 m a/khz) f + i dd m adc 4. data labelled atypo is not to be used for design purposes but is intended as an indication of the ic's potential performance. 5. the formulas given are for the typical characteristics only at 25 c. 6. to calculate total supply current at loads other than 50 pf: i t (c l ) = i t (50 pf) + (c l 50) vfk where: i t is in m a (per package), c l in pf, v = (v dd v ss ) in volts, f in khz is input frequency, and k = 0.002.
mc14518b http://onsemi.com 4 ????????????????????????????????? ????????????????????????????????? switching characteristics (7.) (c l = 50 pf, t a = 25 c) all types characteristic symbol v dd min typ (8.) max unit output rise and fall time t tlh , t thl = (1.5 ns/pf) c l + 25 ns t tlh , t thl = (0.75 ns/pf) c l + 12.5 ns t tlh , t thl = (0.55 ns/pf) c l + 9.5 ns t tlh , t thl 5.0 10 15 e e e 100 50 40 200 100 80 ns propagation delay time clock to q/enable to q t plh , t phl = (1.7 ns/pf) c l + 215 ns t plh , t phl = (0.66 ns/pf) c l + 97 ns t plh , t phl = (0.5 ns/pf) c l + 75 ns t plh , t phl 5.0 10 15 e e e 280 115 80 560 230 160 ns reset to q t phl = (1.7 ns/pf) c l + 265 ns t phl = (0.66 ns/pf) c l + 117 ns t phl = (0.66 ns/pf) c l + 95 ns t phl 5.0 10 15 e e e 330 130 90 650 230 170 ns clock pulse width t w(h) t w(l) 5.0 10 15 200 100 70 100 50 35 e e e ns clock pulse frequency f cl 5.0 10 15 e e e 2.5 6.0 8.0 1.5 3.0 4.0 mhz clock or enable rise and fall time t thl , t tlh 5.0 10 15 e e e e e e 15 5 4 m s enable pulse width t wh(e) 5.0 10 15 440 200 140 220 100 70 e e e ns reset pulse width t wh(r) 5.0 10 15 280 120 90 125 55 40 e e e ns reset removal time t rem 5.0 10 15 5 15 20 45 15 5 e e e ns 7. the formulas given are for the typical characteristics only at 25 c. 8. data labelled atypo is not to be used for design purposes but is intended as an indication of the ic's potential performance. figure 1. power dissipation test circuit and waveform pulse generator variable width c l c l c l c l v dd v ss v ss 500 m f 0.01 m f ceramic 20 ns 50% 10% 90% 20 ns i d q3 q2 q1 q0 c e r
mc14518b http://onsemi.com 5 figure 2. switching time test circuit and waveforms pulse generator c l c l c l c l v dd v ss q3 q2 q1 q0 c e r 20 ns q t r t f v dd v ss 20 ns clock input 90% 50% 10% t wl t wh 90% 50% 10% t plh t phl figure 3. timing diagram 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 14 3 0 9 8 7 6 5 4 3 2 1 clock enable reset q0 q1 q2 q3 q0 q1 q2 q3 mc14518b mc14520b
mc14518b http://onsemi.com 6 figure 4. decade counter (mc14518b) logic diagram (1/2 of device shown) d c r q q d c r q q d c r q q d c r q q q0 q1 q2 q3 reset enable clock figure 5. binary counter (mc14520b) logic diagram (1/2 of device shown) d c r q q d c r q q d c r q q d c r q q q0 q1 q2 q3 reset enable clock
mc14518b http://onsemi.com 7 package dimensions pdip16 p suffix plastic dip package case 64808 issue r notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. a b f c s h g d j l m 16 pl seating 18 9 16 k plane t m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 soic16 dw suffix plastic soic package case 751g03 issue b d 14x b 16x seating plane s a m 0.25 b s t 16 9 8 1 h x 45 m b m 0.25 h 8x e b a e t a1 a l c notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not inlcude mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.13 total in excess of the b dimension at maximum material condition. dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 10.15 10.45 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 0 7
mc14518b http://onsemi.com 8 package dimensions h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 0.78 --- 0.031 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). m l detail p view p c a b e m 0.13 (0.005) 0.10 (0.004) 1 16 9 8 d z e a b c d e e l m z soeiaj16 f suffix plastic eiaj soic package case 96601 issue o on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402745 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc14518b/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk
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